1. Field of Art
Embodiments in the present disclosure generally relate to improved memory architectures. More particular, embodiments relate to implementation of logic, e.g., combinational or sequential logic, connected with a memory on either a common die or connected dice, such that, the logic can process data in the memory and avoid transferring the data outside the memory die or connected set of logic and memory dice.
2. Description of the Background Art
As technology improves, the speed of data processing has increased at an exponential rate. With the improvements have come consumer expectations that applications running on computers would improve at a similar rate.
As processing speed has continued to improve, bottlenecks are becoming apparent in the memory related areas of computer design. For example, latency in accessing memory has become a significant issue in current computer design. Many improvements have been explored in an attempt to address this issue. For example, multiple levels of cache have been used to provide faster access to memory based on how often or recent data has been accessed. For example, some current systems have three levels of cache and a main memory (RAM) in addition to the traditional hard drive disk used to store memory. In such example systems, the first level of cache may only require 4 cycles to access but may only be able to store 64K bytes of data. The second level may require 10 cycles to access, but may be able to store 512K bytes of data. The third level may require 40 cycles to access, but may be able to store 2 MB of data. Random Access Memory (RAM) can store an additional 4-8 GB of data, for example, but may take 6000 cycles to access. But all of these memory components are faster than a hard drive, which may store 100s of GBs of data, but may take 10s or 100s of thousands of cycles to access.